1. Field of the Invention
The present invention relates generally to the field of waveform shaping circuits for performing a clip function, a limit function or any other function, and more particularly to a waveform shaping circuit suitable for use in a function circuit, especially in a delta sigma analog-to-digital converter.
2. Description of Related Art
Electric circuits often employ a variety of waveform shaping circuits including a clip circuit for setting an upper or lower limit of a signal waveform, a limiter circuit composed of a pair of clip circuits for setting both upper and lower limits of a signal waveform, and so on. A known limiter circuit comprises a pair of circuits, each including a diode and a series connected power supply for determining a limit level, connected in parallel with a load coupled between output terminals of a circuit, such that the paired circuits are arranged in parallel with each other with the polarities of their diodes being opposite to each other. To implement a limiter circuit as mentioned above in a semiconductor integrated circuit, diode-connected MOS (metal oxide semiconductor) transistors (hereinafter referred to as the "MOS diode") may be used as the diodes included in the paired circuits. For example, in a function circuit using an operational amplifier, the limiter circuit may be positioned in parallel with a load connected between the output terminal of the operational amplifier and ground, or, in parallel with a feedback circuit from the output terminal to a non-inverting input terminal of the operational amplifier. FIG. 16 illustrates the configuration of the latter circuit having a limiter circuit arranged in parallel with a feedback circuit of an operational amplifier. The illustrated circuit has an input circuit impedance Zin and a feedback circuit impedance Zf and a pair of N-type MOS diodes MD1P and MD2P constituting a limiter circuit as mentioned above is arranged in parallel with the feedback circuit including the feedback circuit impedance Zf. The illustrated limiter has limit levels determined by threshold voltages of the N-type MOS diodes themselves and functions to limit an output voltage of the operational amplifier within a range of a reference voltage (a potential at a non-inverting input terminal of the operational amplifier, for example, ground).+-. the threshold voltage.
In a limiter used in connection with an operational amplifier as mentioned above, an ON-OFF switching speed of a limiting operation is susceptible to the influence of the impedance of a circuit arranged in parallel with the limiter circuit, i.e., the feedback circuit impedance Zf in the example of FIG. 16. Such parallel impedance may cause a reduced switching speed of the limiter. In addition, an equivalent impedance of the MOS diodes acts on the parallel impedance, i.e., a load impedance or a feedback impedance which would result in changes in the impedance constant. The changes in the constant cause a problem that the function circuit using the operational amplifier derives inaccurate results of the functional operation. Furthermore, since the foregoing limiter is configured to directly limit the output voltage of the operational amplifier, the limiter is required to handle an output voltage having a large load driveability, i.e., a relatively large output current. This requires MOS diodes having a sufficiently large gate width to stand such a large current. However, a larger gate width implies a problem that a larger chip area is required when the MOS diodes are implemented in a semiconductor circuit. The problems associated with the limiter are commonly applied to clip circuits.
Analog-to-digital converters utilizing delta sigma modulators have used delta sigma modulators of orders higher than two because such higher order delta sigma modulators more effectively shift quantization noise to out-of-band frequencies. As disclosed in U.S. Pat. No. 5,012,244 (Wellard et al.) entitled "DELTA-SIGMA MODULATOR WITH OSCILLATION DETECT AND RESET CIRCUIT", extension to higher order delta sigma modulators results in stability problems. FIG. 21 herein labeled "prior art" shows the circuit in FIG. 1 of the Wellard et al. patent, in which the disclosed fourth order delta sigma modulator uses an oscillation comparator 30 to detect the signal at the output of the second integrator which, according to the Wellard et al. disclosure is the first one to approach an instability condition. If such instability condition is detected, the oscillation detect comparator short circuits the output of each of the four integrators to its respective input to thereby reset all four integrators and eliminate any accumulated information therein.
A problem with the circuit disclosed in the Wellard et al. patent is that instability of the delta sigma modulator loop does not necessarily always appear at the output of the second stage of integration 12, to which the input of the "oscillation detect comparator" 30 is connected. Consequently, an instability that occurs at the output of a subsequent integrator in the loop will not be detected. Another problem is that when the switches SW1-4 in FIG. 1 of the Wellard et al. patent close that effectively changes the delta sigma loop into a first order loop and the loop output becomes zero, requiring a considerable amount of time. This constitutes a drastic change in the delta modulator circuit during analog-to-digital conversion, and prevents continuous operation. Furthermore, the circuit required to generate the "oscillation threshold" voltage and the "oscillation detector comparator circuit" 30 will occupy an undesirably large amount of chip area.
U.S. Pat. No. 4,509,037 (Harris) entitled "ENHANCED DELTA MODULATION ENCODER" discloses a clipper circuit which is connected between the input and output of one of the integration stages of a high order delta sigma modulator, which, when large signals are present, shorts out the integrator to change the poles and zeroes and hence the characteristics of the filter system. The circuit for accomplishing this is shown in FIG. 3 of the Harris patent and in reproduced as FIG. 22 herein labeled "prior art". A problem of the circuit disclosed in the Harris patent is that the delta sigma modulator is necessarily changed to a first order delta sigma modulator loop when the singular clipping circuit connected between the input of the second integrator and the output of the Nth integrator (equal to the output of the spectrum tilter) is active, due to a phase lag of the output of the spectrum tilter. Therefore, a drastic change in the delta sigma modulator occurs when the clipping circuit turns on and off, and this prevents continuous operation.
Thus, there is an unmet need for an improved circuit and technique for avoiding instability in various circuits, including higher order delta sigma modulators.